1. Field of the Invention
The present relates to the manufacture of semiconductor devices. More particularly, the present invention relates to techniques for improving the reliability of semiconductor device interconnect metallization lines.
2. Description of the Related Art
Interconnect structures of integrated circuits (ICs) generally take the form of patterned metallization lines that are used to electrically interconnect devices and to provide interconnection with external circuitry. By way of example, IC devices may include metal oxide semiconductor ("MOS") devices having diffused source and drain regions separated by channel regions, and gates located over the channel regions. In practice, an IC chip may include thousands or millions of devices, such as MOS transistors.
Conventionally, a dielectric layer (e.g., silicon oxide) is deposited over the devices, and via holes are patterned and formed through the dielectric layer to the devices below. As is well known in the art, photolithography "patterning" is typically accomplished by spin-coating a photoresist layer over the dielectric layer, selectively exposing the photoresist to light through a patterned reticle having via hole patterns, developing the photoresist to form a resist via mask, and etching the exposed dielectric layer to form via holes leading to a lower level. Once the via holes are formed, a conductive material such as tungsten may be used to fill the via holes to define what are known as "W" tungsten plugs. Once the tungsten plugs are formed, a metallization layer is formed over the dielectric layer and the tungsten plugs. The metallization layer is then patterned using conventional photolithography techniques to define a first level of interconnect metal routing. This process may then be repeated if additional layers of metallization lines are desired.
In the design of any integrated circuit device, strong consideration is generally placed on examining the degree of expected electromigration that may occur in view of a metallization line's current carrying requirements. This is typically required because designers know that if too much electromigration occurs in a given metallization line having a particular width, serious reliability impacting voids may form. Accordingly, designers are commonly required to increase a metallization line's width when high levels of current are anticipated, such as, for example, in power and ground bus lines.
In certain circumstances, the designer is forced to make particular metallization lines exceedingly wide, just to prevent the possibility of excessive voiding from occurring. Widening metallization lines does, however, impose a cost penalty since this will require semiconductor chips to be larger than may be necessary to carry out the integrated circuit's designed function.
Electromigration is commonly understood to be the result of an average current flow through a conductor. The flowing electrons transfer a fraction of their momentum to the metal atoms from the scattering process. This momentum transfer in turn causes a movement of the metal atoms (i.e., mass transfer) in the direction of electron flow. Therefore, the amount of momentum transfer, and resulting metal flow, increases with increasing current density. This flow of material is seldom uniform and regions of tensile stress develop where there is a net loss of material over time and regions of compressive stress develop where there is a new increase of material over time. The development of regions of tensile and compressive stress therefore create stress gradients. These stress gradients also cause a flow of metal since stress drives a flow from regions of high stress (i.e., compressive stress) to regions of low stress (i.e., tensile stress).
To pictorially illustrate electromigration problem, FIG. 1 shows a cross-section of a semiconductor substrate 10 having a plurality of conventionally fabricated layers. The semiconductor substrate 10 may include diffusion regions 12 and a polysilicon gate 14 formed over a gate oxide that is defined over the semiconductor substrate 10. A first dielectric layer 19 is formed over the semiconductor substrate 10 and is then planarized. Once planarized, via holes are formed through the first dielectric layer 19, and a conductive via 16 is defined. Next, a metallization layer is deposited and patterned over the first dielectric layer to define a first level of interconnect lines 24. The process is again repeated to form a second dielectric layer 22, conductive vias 18a and 18b, and a second level of interconnect lines 26.
Once the structure is complete, a current "I" having a given current density may be passed through the interconnect structure formed by the first and second levels of interconnect lines 24 and 26, and the conductive vias. Therefore, when current flows that are typical in interconnect lines, such as power lines "Vdd" and ground lines "Vss," are passed through this interconnect structure, the electron flow "e" may unfortunately cause electromigration voids 30 in the interconnect lines 24 and 26. For more information on electromigration and the degrading effects of electromigration, reference may be made to a article entitled "Effects of W-Plug Via Arrangement on Electromigration Lifetime of Wide Line Interconnects," by S. Skala and S. Bothra, Proceedings of the International Interconnect Technology Conference, San Francisco, Calif., June (1998). This article is hereby incorporated by reference.
As shown, the electromigration voids 30 are most commonly formed at the beginning of an interconnect line. This is believed to occur because electromigration degradation is more likely to stop when the sum of electromigration and stress is zero, which will more likely occur at the end of a line. Early observations of electromigration flow and its tendency to stop when a line is relatively short (e.g., a short distance to its terminating end) and continue when a line is relatively long (e.g., a long distance to its terminating end), was first reported by I. A. Blech. The behavior of electromigration defined in terms of the length of a metallization line has thus become widely referred to as the "Blech effect." That is, when a metallization line is at least as short as a given Blech length (also referred to as "critical length") for a particular width, electromigration voids 30 will no longer form. For more information on Blech effect and Blech length, reference may be made to an article entitled "Electromigration and Stress-Induced Voiding in Fine Al and Al-alloy Thin-Film Lines," by C. K. Hu, K. P. Rodbell, T. D. Sullivan, K. Y. Lee and D. P. Bouldin, IBM Journal of Research and Development, Vol. 39, No. 4, July 1995, pp. 465-497. This article is hereby incorporated by reference.
Although this has been widely known, this concept is generally not applicable for many of the interconnect metallization lines and power buses because such lines are generally required to be longer than the Blech length in order to meet functional specifications. As a result, designers have continued to design certain metallization lines wider than necessary in order to prevent void 30 formation which may introduce open circuits or complete functional failures.
In view of the foregoing, there is a need for integrated circuit metallization line structures that are more resistant to electromigration forming voids, without necessitating the design of exceedingly wider metallization lines.